1. Technical Field
The present disclosure relates to a communication code and a corresponding electronic component. More particularly, the present invention relates to a double quasi-cyclic low density parity check (DQC-LDPC) code and a corresponding processor.
2. Description of Related Art
With advances in communication coding technology, error correcting codes have been widely used in various data communication technologies, such as digital video broadcasting (DVB) systems, digital televisions (DTVs), digital set top boxes (STBs), tablet computers, smart phones, and NAND flash memories.
With respect to error correcting codes, the error correction capability of the low-density parity check (LDPC) code is better than the error correction capabilities of the Bose-Chaudhuri-Hocquenghem code (BCH code), the Reed-Solomon code (R-S code), and the convolutional code in a low signal-to-noise (SNR) channel.
Generally, the error correction capability of an LDPC code is decided by the arrangement of value “0” and value “1” in the parity-check matrix. A typical parity-check matrix of an LDPC code used today is designed with a random arrangement of value “0” and value “1.” However, the encoder/decoder of such an LDPC code is complex and therefore difficult to realize.
Thus, a parity-check matrix of an LDPC code with a higher regularity is desired.